Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-19
Clock 3 (C3)
The MCF5206e increments A0 to address the next byte of the word transfer. The selected
device(s) places the second byte of the addressed data onto D[31:24] and asserts the
transfer acknowledge (TA). At the end of C3, the MCF5206e samples the level of TA and
if TA
is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of
the word read is complete and the transfer is terminated. If TA
is negated, the MCF5206e
continues to sample TA and inserts wait states instead of terminating the transfer. The
MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted.
6.5.3 Bursting Write Transfers: Word, Longword, and Line
The MCF5206e uses line-write transfers to access a 16-byte operand for a MOVEM
instruction, when appropriate. A line write accesses a block of four longwords, aligned to
a longword memory boundary, by supplying a starting address that points to one of the
longwords and increments A[3], A[2], A[1], and A[0] of the supplied address for each
transfer. A longword write accesses a single longword aligned to a longword boundary
and increments A[1] and A[0] if the accessed port size is smaller than 32 bits. A word write
accesses a single word of data, aligned to a word boundary and increments A0 if the
accessed port size is smaller than 16 bits. Table 6-9 lists the encodings for the SIZx bits
for each port size for transfers where bursting is both enabled and disabled.
Figure 6-10 is a flowchart for bursting write transfers to 8-, 16-, or 32-bit ports. Bus
operations are similar for each case and vary only with the size indicated, the portion of
the data bus used for the transfer and the specific number of cycles needed for each
transfer. A bursted write transfer can be from two to sixteen transfers long. The flowchart
in Figure 6-10 is for a bursting transfer of four transfers long.
Table 6-9. SIZx Encoding for Burst- and Bursting-Inhibited Ports
OPERAND
SIZE
32-BIT PORT 16 -BIT PORT 8-BIT PORT
BURSTING
ENABLED
BURSTING
INHIBITED
BURSTING
ENABLED
BURSTING
INHIBITED
BURSTING
ENABLED
BURSTING
INHIBITED
SIZ[1] SIZ[0] SIZ[1] SIZ[0] SIZ[1] SIZ[0] SIZ[1] SIZ[0] SIZ[1] SIZ[0] SIZ[1] SIZ[0]
BYTE 010101010101
WORD101010101001
LONGWORD000000100001
LINE 110011101101
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or
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