Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-21
Figure 6-11 shows a user data bursting line-write transfer to a 32-bit port.
Figure 6-11. Line-Write Transfer to a 32-Bit Port (No Wait States)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type. Access type and mode (ATM) identifies the transfer as data. The
read/write (R/W) signal is driven low for a write cycle, and the size signals (SIZ[1:0]) are
driven to $3 to indicate a line transfer. The MCF5206e asserts transfer start (TS) to
indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM low to identify the transfer as user,
and places the data on the data bus (D[31:0]). The selected device(s) asserts the transfer
acknowledge (TA) if it is ready to latch the data. At the end of C2, the selected device
latches the current value of D[31:0], and the MCF5206e samples the level of TA. If TA is
asserted, the transfer of the first longword is complete. If TA is negated, the MCF5206e
TS
A[27:4]
R/W
CLK
TT[1:0]
AT M
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$3
$0
C3 C4
$ADDR
C5
A[3:2]
$2 $3 $0 $1
A[1:0]
ATA
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