Datasheet

Bus Operation
6-22 MCF5206e USER’S MANUAL MOTOROLA
continues to output the data and inserts wait states instead of terminating the transfer. The
MCF5206e continues to sample TA on successive rising edges of CLK until it is asserted.
Clock 3 (C3)
The MCF5206e increments A[3:2] to address the next longword of the line transfer and
drives D[31:0] with the second longword of data. The selected device(s) asserts the TA if
it is ready to latch the data. At the end of C3, the MCF5206e samples the level of TA and
if TA is asserted, the second longword transfer of the line write is complete. If TA is
negated, the MCF5206e continues to sample TA and inserts wait states instead of
terminating the transfer. The MCF5206e continues to sample TA on successive rising
edges of CLK until it is asserted.
Clock 4 (C4)
This clock is identical to C3 except that once TA is asserted, the value corresponds to the
third longword of data for the burst.
Clock 5 (C5)
This clock is identical to C3 except that once TA is asserted, the data value corresponds
to the fourth longword of data for the burst. This is the last CLK cycle of the line-write
transfer and the MCF5206e three-states D[31:0] at the start of the next CLK cycle.
6.5.4 Burst-Inhibited Read Transfer: Word, Longword, and Line
If the burst-enable bit in the appropriate control register (Chip Select Control Register or
Default Memory Control Register) is cleared and the operand size is larger than the port
size of the memory being accessed, the MCF5206e performs word, longword, and line
transfers in burst-inhibited mode. When burst-inhibit mode is selected, the size of the
transfer (indicated by SIZ[1:0]) reflects the port size if the operand being read is larger
than the port size or the operand size if the port size is larger than the operand size. A
transfer size of line (SIZ[1:0] = $3) is never indicated in burst-inhibited mode. If the
operand size is line, the size pins (SIZ[1:0]) always indicate the port size. Refer to Table
6-9 for SIZx encodings for each port size for burst-inhibited transfers.
NOTE
All transfers to DRAM that have an operand size larger than
the port size are bursted. Burst-inhibited transfers cannot be
generated for DRAM accesses.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...