Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-25
Figure 6-13 shows a burst-inhibited supervisor code longword-read transfer from an 8-bit
port.
Figure 6-13. Burst-Inhibited Longword Read From an 8-Bit Port (No Wait States)
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and drives ATM high to identify the transfer as code. The read/write
(R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to
$1 to indicate a byte transfer. The MCF5206e asserts TS to indicate the beginning of a
bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS and drives ATM high to identify the transfer as
supervisor. The selected device(s) places the first byte of the addressed data onto
D[31:24] and asserts TA. At the end of C2, the MCF5206e samples the level of TA and if
TA is asserted, latches the current value of D[31:24]. If TA is asserted, the transfer of the
first byte of the longword read is complete. If TA is negated, the MCF5206e continues to
TS
A[27:2]
R/W
CLK
TT[1:0]
AT M
TA
D[31:24]
TEA
SIZ[1:0]
C1 C2
$1
$0
C3
$ADDR
C4
A[1:0]
$0 $1
$2
$3
C5 C6 C7 C8
ATA
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