Datasheet

Bus Operation
6-26 MCF5206e USER’S MANUAL MOTOROLA
sample TA and inserts wait states instead of terminating the transfer. The MCF5206e
continues to sample TA on successive rising edges of CLK until it is asserted.
Clock 3 (C3)
The MCF5206e increments A[1:0] to address the second byte of the longword transfer.
The MCF5206e continues to drive transfer type (TT[1:0]), read/write (R/W) and size
(SIZ[1:0]) signals to indicate a byte read. Access transfer mode (ATM) is driven high to
indicate the transfer as code. The MCF5206e asserts TS to indicate the beginning of the
second transfer of the bus cycle.
Clock 4 (C4)
This clock is identical to C2 except that once TA is recognized asserted, the latched value
corresponds to the second byte of data for the longword transfer.
Clock 5 (C5)
This clock is identical to C3 except the address is incremented to address the third byte
of the longword transfer.
Clock 6 (C6)
This clock is identical to C2 except that once TA is recognized asserted, the latched value
corresponds to the third byte of data for the longword transfer.
Clock 7 (C7)
This clock is identical to C3 except the address is incremented to address the fourth byte
of the longword transfer.
Clock 8 (C8)
This clock is identical to C2 except that once TA is recognized asserted, the latched value
corresponds to the fourth byte of data for the longword. This is the last CLK cycle of the
longword-read transfer. The selected device negates TA signal and three-states D[31:24]
after the next rising edge of CLK.
6.5.5 Burst-Inhibited Write Transfer: Word, Longword, and Line
The basic transfer of a burst-inhibited write is the same as “normal” write with the addition
of more transfers until the entire operand has been accessed. Burst-inhibited write
transfers can be from two to 16 transfers long. Figure 6-14 is a flowchart for burst-inhibited
write transfers (4 transfers long) to 8-, 16-, or 32-bit ports. Bus operations are similar for
each case and vary only with the size indicated, the portion of the data bus used for the
transfer, and the specific number of cycles needed for each transfer.
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