Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-29
the data and inserts wait states instead of terminating the transfer. The MCF5206e
continues to sample TA on successive rising edges of CLK until it is asserted.
Clock 3 (C3)
The MCF5206e increments A[1:0] to address the next word, asserts TS and drives ATM
low to identify the transfer as code or data.
Clock 4 (C4)
This clock is identical to C2 except that the data driven corresponds to the second word
of data. This is the last CLK cycle of the longword-write transfer and the MCF5206e three-
states D[31:0] at the start of the next CLK cycle.
6.5.6 Asynchronous-Acknowledge Read Transfer
The MCF5206e provides an asynchronous acknowledge that can be used for termination
of all MCF5206e transfers except accesses to DRAM. ATA is synchronized internally
before being used. If recognition by a specific CLK rising edge is required, ATA must meet
the specified setup and hold times to CLK. Because of the internal synchronization of
ATA, data must be driven on the bus until the asynchronous transfer acknowledge is
recognized internally. If transfer error acknowledge (TEA) is asserted while ATA is being
synchronized internally, the transfer terminates in an error.
NOTE
The internal synchronized version of (ATA) is referred to as
‘‘internal asynchronous transfer acknowledge.’’ Because of
the time required to internally synchronize ATA during a read
cycle, data is latched on the rising edge of CLK when the
internal asynchronous transfer acknowledge is asserted.
Consequently, data must remain valid for at least one and half
CLK cycles after the assertion of ATA
. Similarly, during a write
cycle, data is driven until the falling edge of CLK when the
internal asynchronous transfer acknowledge is asserted.
Figure 6-16 is a flowchart for read transfers to 8-, 16-, or 32-bit ports with asynchronous
termination. Bus operations are similar for each case and vary only with the size indicated,
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