Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-31
Figure 6-17 shows a user code byte read from an 8-bit port.
Figure 6-17. Byte-Read Transfer from an 8-Bit Port Using Asynchronous
Termination (One Wait State)
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as code. The read/write (R/W) signal
is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate
a byte transfer. The MCF5206e asserts TS to indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS and drives ATM low to identify the transfer as user.
The selected device(s) asserts ATA with the required setup time prior to the falling clock
edge.
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
ATA
D[31:24]
TEA
SIZ[1:0]
C1 C2
$1
$0
$ADDR
C3
TA
INTERNAL ATA
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