Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-33
Figure 6-19 shows a user data byte transfer to a 32-bit port with asynchronous
termination.
Figure 6-19. Byte-Write Transfer to a 32-Bit Port Using Asynchronous Termination
(One Wait State)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as data. The read/write (R/W) signal
is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a
byte transfer. The MCF5206e asserts TS to indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM low to identify the transfer as user
and places the data on the data bus (D[31:0]). The selected slave device asserts ATA
prior to the falling edge of the clock. The selected slave device may latch the data present
on the data bus or may wait until the end of Clock 3 (after internal asynchronous transfer
acknowledge has been asserted).
TS
A[27:0]
R/W
CLK
TT[1:0]
ATM
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$0
C3
$ADDR
ATA
$1
INTERNAL ATA
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