Datasheet

Bus Operation
6-34 MCF5206e USER’S MANUAL MOTOROLA
Clock 3 (C3)
At the end of C3, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, the transfer of the byte is complete and the transfer
terminates. If internal asynchronous transfer acknowledge is negated, the MCF5206e
continues to sample internal asynchronous transfer acknowledge and inserts wait states
instead of terminating the transfer. The MCF5206e continues to sample internal
asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior
to the falling edge of C2 meeting the setup time requirement, internal asynchronous
transfer acknowledge is asserted by the rising edge of C3.
6.5.8 Bursting Read Transfers: Word, Longword, and Line with
Asynchronous Acknowledge
If the burst-enable bit in the appropriate Chip Select Control Register (CSCR) or Default
Memory Control Register (DMCR) is set to 1 and the operand size is larger than the port
size of the memory being accessed, the MCF5206e performs word, longword, and line
transfers in burst mode. When burst mode is selected and the transfer is not to DRAM,
the transfer can be terminated synchronously using TA
, or asynchronously using ATA.
The transfer attributes are the same for both the synchronous and asynchronously
terminated burst transfers.
Figure 6-20 is a flowchart for bursting read transfers to 8-, 16-, or 32-bit ports using
asynchronous termination. Bus operations are similar for each case and vary only with the
size indicated, the portion of the data bus needed for the transfer, and the specific number
of cycles used for each transfer. A bursted transfer can be from two to 16 transfers long.
Fr
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Freescale Semiconductor, Inc.
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