Datasheet

Bus Operation
6-36 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-21 shows a bursting supervisor data longword-read transfer from a 16-bit port.
Figure 6-21. Bursting Longword-Read from 16-Bit Port Using Asynchronous
Termination (One Wait State)
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as reading data. The read/write
(R/W) signal is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to
$0 to indicate a longword transfer. The MCF5206e asserts TS to indicate the beginning of
a bus cycle.
TS
A[27:2]
R/W
CLK
TT[1:0]
ATM
ATA
D[31:16]
TEA
SIZ[1:0]
C1 C2
$0
$0
C3
$ADDR
C4 C5
A[1]
A[0]
TA
INTERNAL ATA
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eescale S
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