Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-37
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM high to identify the transfer as
supervisor. The selected device(s) asserts ATA prior to the falling edge of the clock.
Clock 3 (C3)
At the end of C3, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, latches the current value of D[31:16]. If internal
asynchronous transfer acknowledge is asserted, the transfer of the first word is complete.
If internal asynchronous transfer acknowledge is negated, the MCF5206e continues to
sample internal asynchronous transfer acknowledge and inserts wait states instead of
terminating the transfer. The MCF5206e continues to sample internal asynchronous
transfer acknowledge until it is asserted. As long as ATA
is asserted prior to the falling
edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge
of C3.
Clock 4 (C4)
The MCF5206e increments A[1:0] to address the next word. The selected device(s)
asserts ATA
prior to the falling edge of the clock.
Clock 5 (C5)
At the end of C5, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, latches the current value of D[31:16]. If internal
asynchronous transfer acknowledge is asserted, the transfer of the second word is
complete and the transfer is terminated. If internal asynchronous transfer acknowledge is
negated, the MCF5206e continues to sample internal asynchronous transfer
acknowledge and inserts wait states instead of terminating the transfer. The MCF5206e
continues to sample internal asynchronous transfer acknowledge until it is asserted. As
long as ATA is asserted prior to the falling edge of C4, internal asynchronous transfer
acknowledge is asserted by the rising edge of C5.
6.5.9 Bursting Write Transfers: Word, Longword, and Line with
Asynchronous Acknowledge
Figure 6-22 is a flowchart for bursting write transfers (four transfers long) to 8-, 16-, or 32-
bit ports using asynchronous termination. Bus operations are similar for each case and
vary only with the size indicated, the portion of the data bus used for the transfer, and the
specific number of cycles needed for each transfer. A bursted transfer can be from two to
16 transfers long.
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eescale S
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Freescale Semiconductor, Inc.
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