Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-39
Figure 6-23 shows a bursting user data line-write transfer to a 32-bit port using
asynchronous termination.
Figure 6-23. Bursting Line-Write from 32-Bit Port Using Asynchronous Termination
(One Wait State)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as data. The read/write (R/W) signal
is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $3 to indicate a
line transfer. The MCF5206e asserts TS to indicate the beginning of a bus cycle.
TS
A[27:4]
R/W
CLK
TT[1:0]
AT M
ATA
D[31:0]
TEA
SIZ[1:0]
C1
C2
$3
$0
C3 C4 C5
C6 C7 C8
C9
$ADDR
A[3:2]
$0
A[1:0]
$1 $2 $3
TA
INTERNAL ATA
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eescale S
emiconduct
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