Datasheet

Bus Operation
6-40 MCF5206e USER’S MANUAL MOTOROLA
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM low to identify the transfer as user and
places the data on the data bus (D[31:0]). The selected device(s) asserts ATA if it is ready
to latch the data, which is recognized by the MCF5206e on the next falling clock edge.
Clock 3 (C3)
If the selected device asserted asynchronous transfer acknowledge during C2, the
selected device must latch the data by the end of C3. At the end of C3, the MCF5206e
samples the level of internal asynchronous transfer acknowledge. If internal
asynchronous transfer acknowledge is asserted, the transfer of the first longword is
complete. If internal asynchronous transfer acknowledge is negated, the MCF5206e
continues to sample internal asynchronous transfer acknowledge and inserts wait states
instead of terminating the transfer. The MCF5206e continues to sample internal
asynchronous transfer acknowledge until it is asserted. As long as ATA is asserted prior
to the falling edge of C2, the internal asynchronous transfer acknowledge is asserted by
the rising edge of C3.
Clock 4 (C4)
The MCF5206e increments A[3:2] to address the next longword of the line transfer and
drives D[31:0] with the second longword of data. The selected device(s) asserts ATA if it
is ready to latch the data. At the end of C4, the MCF5206e samples the level of internal
ATA and if it is asserted, the second longword transfer of the line write is complete. If
internal ATA is negated, the MCF5206e continues to sample internal ATA and inserts wait
states instead of terminating the transfer. The MCF5206e continues to sample internal
ATA on successive falling edges of the CLK until it is asserted.
Clock 5 (C5)
This clock is identical to C3 except that the data value corresponds to the second
longword of data for the burst.
Clock 6 (C6)
This clock is identical to C4 except that once internal ATA is asserted, the address and
the data values correspond to the third longword of data for the burst.
Clock 7 (C7)
This clock is identical to C3 except that the data value corresponds to the third longword
of data for the burst.
Clock 8 (C8)
This clock is identical to C4 except that once internal ATA is asserted the address and
data value correspond to the fourth longword of data for the burst.
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