Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-41
Clock 9 (C9)
This clock is identical to C3 except that the data value corresponds to the fourth longword
of data for the line. This is the last CLK cycle of the line write transfer and the MCF5206e
three-states D[31:0] at the start of the next CLK cycle.
6.5.10 Burst-Inhibited Read Transfers: Word, Longword, and Line with
Asynchronous Acknowledge
If the burst-enable bit is cleared in the appropriate Chip Select Control Register (CSCR)
or Default Memory Control Register (DMCR) and the operand size is larger than the port
size of the memory being accessed, the MCF5206e performs word, longword, and line
transfers in burst-inhibited mode. When burst-inhibit mode is selected, the size of the
transfer (indicated by SIZ[1:0]) reflects the port size if the operand being read is larger
than the port size, or the operand size if the port size is larger than the operand size. A
transfer size of line (SIZ[1:0] = $3) is never indicated in burst-inhibited mode. If the
operand size is line, the size pins (SIZ[1:0]) always indicates the port size.
The basic transfer of a burst-inhibited read using asynchronous termination is the same
as “normal” read using asynchronous termination with the addition of more transfers, until
the entire operand has been accessed. Figure 6-24 is a flowchart for burst-inhibited read
transfers to 8-, 16-, or 32-bit ports with asynchronous termination. Bus operations are
similar for each case and vary only with the size indicated, the portion of the data bus used
for the transfer, and the specific number of cycles needed for each transfer. The flowchart
is specifically for a burst-inhibited transfer of four transfers long.
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Freescale Semiconductor, Inc.
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