Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL xiii
8.1.1 Features .....................................................................................8-1
8.2 SIM Operation ......................................................................................8-1
8.2.1 Module Base Address Register (MBAR) ....................................8-1
8.2.2 Bus Timeout Monitor ..................................................................8-2
8.2.3 Spurious Interrupt Monitor ..........................................................8-2
8.2.4 Software Watchdog Timer ..........................................................8-3
8.2.5 Interrupt Controller .....................................................................8-3
8.3 Programming Model .............................................................................8-6
8.3.1 SIM Registers Memory Map .......................................................8-6
8.3.2 SIM Registers .............................................................................8-7
8.3.2.1 Module Base Address Register (MBAR) ........................8-7
8.3.2.2 SIM Configuration Register (SIMR) ................................8-8
8.3.2.3 Interrupt Control Register (ICR) ......................................8-9
8.3.2.4 Interrupt Mask Register (IMR) ......................................8-11
8.3.2.5 Interrupt Pending Register (IPR) ..................................8-12
8.3.2.6 Reset Status Register (RSR) ........................................8-13
8.3.2.7 System Protection Control Register (SYPCR) ..............8-13
8.3.2.8 Software Watchdog Interrupt Vector Register (SWIVR) 8-15
8.3.2.9 Software Watchdog Service Register (SWSR) .............8-16
8.3.2.10 Pin Assignment Register (PAR) ....................................8-16
8.4 Bus Arbitration Control .......................................................................8-18
8.4.1 Bus Master Arbitration Control (MARB) ...................................8-18
Section 9
Chip-Select Module
9.1 Introduction ...........................................................................................9-1
9.1.1 Features .....................................................................................9-1
9.2 Chip Select Module I/O ........................................................................9-1
9.2.1 Control Signals ...........................................................................9-1
9.2.1.1 Chip Select (CS[7:0]) ......................................................9-1
9.2.1.2 Write Enable (WE[3:0]) ...................................................9-1
9.2.1.3 Address Bus ...................................................................9-3
9.2.1.4 Data Bus .........................................................................9-4
9.2.1.5 Transfer acknowledge (TA) ............................................9-4
9.3 Chip Select Operation ..........................................................................9-4
9.3.1 Chip Select Bank Definition ........................................................9-5
9.3.1.1 Base Address and Address masking ..............................9-5
9.3.1.2 Access Permissions ........................................................9-6
9.3.1.3 Control Features .............................................................9-6
9.3.2 Global Chip Select Operation .....................................................9-8
9.3.3 General Chip Select Operation ..................................................9-8
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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