Datasheet

Bus Operation
6-44 MCF5206e USER’S MANUAL MOTOROLA
Clock 3 (C3)
At the end of C3, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, latches the current value of D[31:24]. If internal
asynchronous transfer acknowledge is asserted, the transfer of the first byte is complete.
If internal asynchronous transfer acknowledge is negated, the MCF5206e continues to
sample internal asynchronous transfer acknowledge and inserts wait states instead of
terminating the transfer. The MCF5206e continues to sample internal asynchronous
transfer acknowledge until it is asserted. As long as ATA is asserted prior to the falling
edge of C2, internal asynchronous transfer acknowledge is asserted by the rising edge
of C3.
Clock 4 (C4)
This clock is identical to C1 except the address bus is incremented to point to the second
byte of data.
Clock 5 (C5)
This clock is identical to C2.
Clock 6 (C6)
This clock is identical to C3 except once internal ATA is recognized, the data corresponds
to the second byte of data.
6.5.11 Burst-Inhibited Write Transfers: Word, Longword, and Line with
Asynchronous Acknowledge
The basic transfer of a burst-inhibited write using asynchronous termination is the same
as “normal” write transfers with asynchronous termination but with the addition of more
transfers until the entire operand has been accessed. Figure 6-26 is a flowchart for burst-
inhibited write transfers to 8-, 16-, or 32-bit ports using asynchronous termination. Bus
operations are similar for each case and vary only with the size indicated, the portion of
the data bus used for the transfer, and the specific number of cycles needed for each
transfer. The flowchart specifically depicts a burst-inhibited transfer of four accesses long.
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