Datasheet

Bus Operation
6-46 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-27 shows a burst-inhibited supervisor data longword-write transfer to a 16-bit
port.
Figure 6-27. Burst-Inhibited Longword-Write Transfer to 16-Bit Port Using
Asynchronous Termination (One Wait State)
Clock 1 (C1)
The write cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as data. The read/write (R/W) signal
is driven low for a write cycle, and the size signals (SIZ[1:0]) are driven to $2 to indicate a
word transfer. The MCF5206e asserts TS to indicate the beginning of a bus cycle.
TS
A[27:2]
R/W
CLK
TT[1:0]
ATM
ATA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$2
$0
C3
C4
$ADDR
C5
C6
A[1]
A[0]
TA
INTERNAL ATA
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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