Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-47
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM high to identify the transfer as
supervisor and drives the data on the data bus (D[31:0]). The selected device(s) asserts
ATA if it is ready to latch the data.
Clock 3 (C3)
At the end of C3, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, terminates the first word transfer. If internal
asynchronous transfer acknowledge is asserted, the transfer of the first word is complete.
If internal asynchronous transfer acknowledge is negated, the MCF5206e continues to
sample internal asynchronous transfer acknowledge and inserts wait states instead of
terminating the transfer. The MCF5206e continues to sample internal asynchronous
transfer acknowledge until it is asserted. As long as ATA is asserted by the falling edge of
C2, the rising edge of C3 asserts the internal asynchronous transfer acknowledge.
Clock 4 (C4)
This clock is identical to C1 except the MCF5206e increments the address to indicate the
next word.
Clock 5 (C5)
This clock is identical to C2 except that the data driven corresponds to the second word
of data.
Clock 6 (C6)
This clock is identical to C3 except after asynchronous transfer acknowledge is
recognized, the MCF5206e three-states the data bus after the next rising edge of CLK.
6.5.12 Termination Tied to GND
If the MCF5206e is in a system with multiple masters and you require zero wait-state
operation, you can tie ATA
to GND to achieve zero wait-state operation for nonDRAM
transfers. ATA
must be used in this case as the MCF5206e can drive TA during external
master accesses. When ATA is tied to GND, all nonDRAM transfers follow the timing
shown with TA
asserted with zero wait states.
If the MCF5206e is the only master in the system, TA
and BG can be tied to GND to grant
mastership of the external bus to the MCF5206e and achieve zero wait-state operation.
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eescale S
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