Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-49
NOTE
External masters that are using internal MCF5206e chip
selects, DRAM, and default memory control signals must
initiate aligned transfers only.
6.7 ACKNOWLEDGE CYCLES
When a peripheral device requires the services of the MCF5206e or is ready to send
information that the ColdFire core requires, it can signal the ColdFire core to take an
interrupt exception. The interrupt exception transfers control to a routine that responds
appropriately. The peripheral device uses the interrupt priority level/interrupt request
signals (IPLx/IRQx) to signal an interrupt condition to the MCF5206e.
The MCF5206e has two levels of interrupt masking. The first level of interrupt masking is
in the interrupt controller in the System Integration Module (SIM) which masks individual
interrupt inputs and then outputs the interrupt priority level of the highest pending
unmasked interrupt to the ColdFire core. The Status Register (SR) provides the second
level of interrupt masking in the ColdFire core. The value of the SR interrupt mask is the
highest priority level that the ColdFire core ignores. When an interrupt request has a
priority higher than the value in the mask, the ColdFire core makes the request a pending
interrupt. For more information about the Status Register refer to Section 3.2.2.1 Status
Register in the ColdFire Core Section.
The MCF5206e continuously samples the external interrupt input signals and
synchronizes and debounces these signals. An interrupt request must be held constant
for at least two consecutive CLK periods to be considered a valid input. If the external
interrupt inputs are programmed to individual interrupt requests (at level 1, 4, and 7), the
interrupt request must maintain the interrupt request level until the MCF5206e
acknowledges the interrupt to guarantee that the interrupt is recognized. If the external
interrupt inputs are programmed to be interrupt priority levels, the interrupt request must
maintain the interrupt request level or a higher priority level until the MCF5206e
acknowledges the interrupt to guarantee that the interrupt is recognized.
NOTE
All interrupts are level sensitive only. Interrupts must remain
stable and held valid for the interrupt to be detected.
The MCF5206e takes an interrupt exception for a pending interrupt within one instruction
boundary after processing any other pending exception with a higher priority. Thus, the
MCF5206e executes at least one instruction in an interrupt exception handler before
recognizing another interrupt request.
If the AVEC bit in the Interrupt Control Register (ICR) for the interrupt being acknowledged
is set to 1 (enabling autovectoring), the interrupt acknowledge vector is generated
internally and no interrupt acknowledge cycle is generated on the external bus. Refer to
the SIM section 7.3.2.3 Interrupt Control Register for ICR programming.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...