Datasheet

Bus Operation
6-50 MCF5206e USER’S MANUAL MOTOROLA
NOTE
If autovector generation is used for external interrupts, no
interrupt acknowledge cycle is generated on the external bus.
Consequently, the user must clear the external interrupt in the
interrupt service routine.
6.7.1 Interrupt Acknowledge Cycle
When the MCF5206e processes an interrupt exception, it performs an interrupt
acknowledge bus cycle to obtain the vector number that contains the starting location of
the interrupt exception handler.
The interrupt acknowledge bus cycle is a read transfer. It differs from a normal read cycle
in the following respects:
• TT[1:0] = $3 to indicate a CPU space/acknowledge bus cycle
• ATM = $1 when TS is asserted and ATM = $0 when TS is negated
• Address signals A[27:5] are set to all ones ($7FFFFF)
• Address signals A[4:2] are set to the interrupt request level being acknowledged
• Address signals A[1:0] are set to all zeros ($0)
The responding device places the vector number on D[31:24] of the data bus during the
interrupt acknowledge bus cycle and the cycle is terminated normally with TA or ATA.
Figure 6-30 and Figure 6-31 illustrate a flowchart and functional timing diagram for an
interrupt-acknowledge cycle terminated with TA.
Figure 6-30. Interrupt-Acknowledge Cycle Flowchart
MCF5206e SYSTEM
1. DRIVE $7FFFFF ON A[27:5]
2. DRIVE $0 ON A[1:0]
3. DRIVE INTERRUPT LEVEL ON A[4:2]
4. DRIVE R/W
TO READ (R/W = 1)
5. DRIVE SIZ[1:0] TO INDICATE BYTE (SIZ1 = $0, SIZ0 =$1)
6. DRIVE TT[1:0] AND ATM TO INDICATE INTERRUPT
ACKNOWLEDGE (TT[1] = TT[0] = $1 AND ATM = $1)
7. ASSERT TS
FOR ONE CLK CYCLE
1. DECODE ADDRESS AND SELECT THE APPROPRIATE SLAVE
DEVICE.*
2. DRIVE DATA ON D[31:24]
3. ASSERT TA
FOR ONE CLK CYCLE
1. REGISTER DATA (D[31:24])
2. RECOGNIZE THE TRANSFER IS DONE
1. NEGATE TS
2. DRIVE ATM TO INDICATE INTERRUPT ACKNOWLEDGE
(ATM = $0)
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