Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-51
Figure 6-31 shows an interrupt acknowledge cycle.
Figure 6-31. Interrupt Acknowledge Bus Cycle Timing (No Wait States)
Clock 1 (C1)
The interrupt acknowledge cycle starts in C1. During C1, the MCF5206e places valid
values on the address bus (A[27:0]) and transfer control signals. The address bus is
driven with $7FFFFF on A[27:5], $0 on A[1:0] and the interrupt level being acknowledged
on A[4:2]. The transfer type (TT[1:0]) signals are driven to $3 and the ATM is driven high
to identify the access as an interrupt acknowledge cycle. The read/write (R/W) signal is
driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $1 to indicate a
byte transfer. The MCF5206e asserts TS to indicate the beginning of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates transfer start (TS), drives access type and mode
(ATM) low to identify the transfer as an interrupt acknowledge cycle. The selected
TS
A[27:5]
R/W
CLK
TT[1:0]
AT M
TA
D[31:24]
TEA
SIZ[1:0]
C1 C2
$1
$3
A[4:2]
$INT_LEVEL
A[1:0]
ATA
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