Datasheet

Bus Operation
6-52 MCF5206e USER’S MANUAL MOTOROLA
device(s) places the interrupt vector number onto D[31:24] and asserts TA. At the end of
C2, the MCF5206e samples the level of TA and if TA is asserted, latches the current value
of D[31:24] which contains the interrupt vector number. If TA is asserted, the transfer of
the interrupt vector is complete and the transfer terminates. If TA is negated, the
MCF5206e continues to sample TA and inserts wait states instead of terminating the
transfer. The MCF5206e continues to sample TA on successive rising edges of CLK until
it is asserted.
NOTE
Interrupt acknowledge cycles can be asynchronously
acknowledged using ATA. As long as ATA is asserted by the
falling edge of C2, internal asynchronous transfer
acknowledge is asserted by the rising edge of C3. The
interrupt vector must remain driven on D[31:24] until internal
asynchronous transfer acknowledge is asserted.
6.8 BUS ERRORS
The system hardware can use the transfer error acknowledge (TEA) signal to abort the
current bus cycle when a fault is detected. A bus error is recognized during a bus cycle
when TEA is asserted.
When the MCF5206e recognizes a bus error condition for an access, the access is
terminated immediately. An access that requires more than one transfer, aborts without
completing the remaining transfers if TEA is asserted, regardless of whether the access
uses burst or burst-inhibited transfers.
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Freescale Semiconductor, Inc.
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