Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
xiv MCF5206e USER’S MANUAL MOTOROLA
9.3.3.1 Nonburst Transfer with no Address Setup or Hold .........9-9
9.3.3.2 Nonburst Transfer With Address Setup ........................9-10
9.3.3.3 Nonburst Transfer With Address Setup and Hold ........9-11
9.3.3.4 Burst Transfer and Chip Selects ...................................9-13
9.3.3.5 Burst Transfer With Address Setup ..............................9-15
9.3.3.6 Burst Transfer With Address Setup and Hold ...............9-17
9.3.4 External Master Chip Select Operation ....................................9-20
9.3.4.1 External Master Nonburst Transfer ..............................9-20
9.3.4.2 External Master Burst Transfer .....................................9-22
9.3.4.3 External Master Burst Transfer with Setup and Hold ...9-24
9.4 Programming Model ...........................................................................9-26
9.4.1 Chip Select Registers Memory Map .........................................9-26
9.4.2 Chip Select Controller Registers ..............................................9-28
9.4.2.1 Chip Select Address Register (CSAR0 - CSAR7) ........9-28
9.4.2.2 Chip Select Mask Register (CSMR0 - CSMR7) ...........9-29
9.4.2.3 Chip Select Control Register (CSCR0 - CSCR7) .........9-31
9.4.2.4 Default Memory Control Register (DMCR) ...................9-38
Section 10
Parallel Port (General Purpose I/O Module)
10.1 Introduction ........................................................................................10-1
10.2 Parallel Port Operation .......................................................................10-1
10.3 Programming Model ...........................................................................10-1
10.3.1 Parallel Port Registers Memory Map .......................................10-1
10.3.2 Parallel Port Registers .............................................................10-2
10.3.2.1 Port A Data Direction Register (PADDR) .....................10-2
10.3.2.2 Port A Data Register (PADAT) .....................................10-2
Section 11
DRAM Controller
11.1 Introduction .........................................................................................11-1
11.1.1 Features ...................................................................................11-1
11.2 DRAM Controller I/O ..........................................................................11-1
11.2.1 Control Signals .........................................................................11-1
11.2.1.1 Row Address Strobes (RAS[0], RAS[1]) .......................11-1
11.2.1.2 Column Address Strobes(CAS[0:3]) .............................11-2
11.2.1.3 DRAM Write (DRAMW) ................................................11-3
11.2.2 Address Bus .............................................................................11-3
11.2.3 Data Bus ..................................................................................11-4
11.3 DRAM Controller Operation ...............................................................11-4
Fr
eescale S
emiconduct
or
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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