Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-55
two-wire mode. In this mode, the active-low bus grant (BG) input of the MCF5206e is
connected to the active-high HOLDREQ output of the external bus master and the active-
low bus-driven (BD) output of the MCF5206e is connected to the active-high HOLDACK
input of the external bus master. Because the external bus master controls the assertion/
negation of HOLDREQ, it controls when the MCF5206e is granted the bus, making the
MCF5206e the lower priority master. You can program the bus lock (BL) bit in the SIM
Configuration Register (SIMR) to a 1, instructing the MCF5206e to retain control of the
external bus, even when bus grant (BG) is negated. This lets you control the priority of the
MCF5206e with respect to the external master when in two-wire mode.
Figure 6-33. MCF5206e Two-Wire Mode Bus Arbitration Interface
When the external master is not using the bus, it negates HOLDREQ driving bus grant
(BG) low, granting the bus to the MCF5206e. When the MCF5206e has an internal bus
request pending and bus grant (BG) is low, the MCF5206e drives BD low, negating
HOLDACK to the external bus master. When the external bus master requires use of the
external bus, it asserts HOLDREQ, driving bus grant (BG) high, requesting the MCF5206e
to relinquish the bus. If bus grant (BG) is negated while a bus cycle is in progress and if
the bus lock bit is cleared, the MCF5206e relinquishes the bus at the completion of the
bus cycle. Note that the MCF5206e considers the individual transfers of a burst or burst-
inhibited access to be a single bus cycle and does not relinquish the bus until the
completion of the last transfer of the series.
When the bus has been granted to the MCF5206e, one of two situations can occur. In the
first case, the MCF5206e has an internal bus request pending, the MCF5206e asserts BD
to indicate explicit bus ownership and begins the pending bus cycle by asserting TS. The
BG
BD
BR
MCF5206e
HOLDREQ
HOLDACK
EXTERNAL BUS MASTER
A[27:0]
R/W
SIZ[1:0]
D[31:0]
TS
TA
ATA
TEA
A[27:0]
R/W
SIZ[1:0]
D[31:0]
TS
TA
ATA
TEA
TO/FROM EXTERNAL MEMORY
AND CONTROL
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Freescale Semiconductor, Inc.
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