Datasheet

Bus Operation

6-56 MCF5206e USER’S MANUAL MOTOROLA

MCF5206e continues to assert BD until the completion of the bus cycle. If bus grant (BG)

is negated by the end of the bus cycle and the Bus Lock bit in the SIMR is 0, the

MCF5206e negates BD. As long as bus grant (BG) is asserted, BD remains asserted to

indicate the bus is owned by the MCF5206e and the MCF5206e continuously drives the

address bus, attributes and control signals.

In the second situation, the bus is granted to the MCF5206e, but the MCF5206e does not

have an internal bus request pending and the Bus Lock bit in the SIMR is 0, so it takes

implicit ownership of the bus. Implicit ownership of the bus occurs when the MCF5206e is

granted the bus, but there are no pending bus cycles and the bus lock bit (BL) in the SIMR

is set to 0. The MCF5206e does not drive the bus and does not assert bus driven BD if

the bus is implicitly owned. If an internal bus request is generated or the bus lock bit in the

SIM Configuration Register (SIMR) is set to 1, the MCF5206e assumes explicit ownership

of the bus. If explicit ownership was assumed because of an internal request being

generated, the MCF5206e immediately begins an access and simultaneously asserts bus

driven BD and TS. If explicit ownership was assumed because of the bus lock bit being

set to 1, the MCF5206e asserts bus driven BD and drives the address, attributes and

control signals but does no assert TS and does not begin a bus transfer.

In the case where the bus lock bit is set to 1, the MCF5206e is the explicit master of the

external bus, but does not begin an access until an internal request is generated. Figure

6-34 illustrates implicit and explicit bus ownership because of the bus lock bit being set

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