Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-57
then an internal bus request being generated.
Figure 6-34. Two-Wire Implicit and Explicit Bus Ownership
In Figure 6-34, the external master has ownership of the external bus during Clock 1 (C1)
and Clock 2 (C2). In Clock 3 (C3) the external master releases control of the bus by
asserting bus grant (BG
) to the MCF5206e. During Clock 4 (C4) and Clock 5 (C5) the
MCF5206e is implicit owner because an internal access is not pending and the bus lock
bit is cleared. In C5, the bus lock bit is set to 1, causing the MCF5206e to take explicit
ownership of the bus in Clock 6 (C6) by asserting BD. In Clock 7 (C7) the external master
removes the bus grant to the MCF5206e. Because the bus lock bit is set to 1, the
MCF5206e does not relinquish the bus (the MCF5206e continues to assert BD
).
NOTE
The MCF5206e can start a transfer during the CLK cycle after
BG is asserted. The external master should not assert BG to
the MCF5206e until it has stopped driving the bus. BG
cannot
be asserted while the external master transfer is still in
progress or damage to the part could occur.
CLK
TS
TRANSFER
TA
D[31:0]
A[27:0]
AT TR IBUT ES
BG
BD
EXTERNAL
MASTER
MCF5206e
BUS LOCK BIT
EXPLICIT OWNERSHIP
IMPLICIT
OWNERSHIP
C1
C2
C3 C4 C5 C6 C7 C8 C9
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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