Datasheet

Bus Operation
6-62 MCF5206e USER’S MANUAL MOTOROLA
MCF5206e, BR, BD, and BG connect to the bus arbiter, allowing the bus arbiter to control
use of the external bus by the MCF5206e.
The MCF5206e requests the bus from the external bus arbiter by asserting bus request
(BR) whenever an internal bus request is pending (the ColdFire core requests an access).
The MCF5206e continues to assert BR
until after the start of the external bus transfer. The
MCF5206e can negate BR
at any time regardless of the bus grant (BG) status. If the bus
is granted to the MCF5206e when an internal bus request is generated, the MCF5206e
asserts bus driven (BD) simultaneously with transfer start, allowing the access to begin
immediately. The MCF5206e always drives BR and BD. They cannot be directly wire-
ORed with other devices.
The external arbiter asserts BG to indicate to the MCF5206e that it has been granted the
bus and may begin a bus cycle after the rising edge of the next CLK. If BG is negated while
a bus cycle is in progress, the MCF5206e relinquishes the bus at the completion of the
bus cycle, except if the bus lock (BL) bit in the SIMR is set. To guarantee that the bus is
relinquished, BL must be cleared and BG must be negated prior to the rising edge of the
CLK in which the last TA, TEA or internal asynchronous transfer acknowledge is asserted.
Note that the MCF5206e considers any series of bus transfers of a burst or a burst-
inhibited transfer to be a single bus cycle and does not relinquish the bus until completion
of the last transfer of the series.
When the bus has been granted to the MCF5206e in response to the assertion of BR, one
of two situations can occur. In the first case, the MCF5206e has an internal bus request
pending, the MCF5206e asserts BD to indicate explicit bus ownership and begins the
pending bus cycle by asserting TS. The MCF5206e continues to assert BD until the
external bus master negates BG, after which BD is negated at the completion of the bus
cycle. As long as BG is asserted, BD remains asserted to indicate the bus is owned by the
MCF5206e and the MCF5206e continuously drives the address bus, attributes and
control signals.
In the second situation, the bus is granted to the MCF5206e, but the MCF5206e does not
have an internal bus request pending and the bus lock bit in the SIMR is cleared. In this
case, the MCF5206e takes implicit ownership of the bus. Implicit ownership of the bus
occurs when the MCF5206e is granted the bus, but there are no pending bus cycles. The
MCF5206e does not drive the bus and does not assert BD
if the bus is implicitly owned.
If an internal bus request is generated or the bus lock bit in the SIMR is set to 1, the
MCF5206e assumes explicit ownership of the bus. If explicit ownership was assumed due
to an internal request being generated, the MCF5206e immediately begins an access and
simultaneously asserts BD
and TS. If explicit ownership was assumed due to the bus lock
bit being set to 1, the MCF5206e asserts BD and drives the address, attributes, and
control signals. In this case, the MCF5206e is the explicit master of the external bus, but
does not begin an access until an internal request is generated. Figure 6-38 illustrates
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...