Datasheet
Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-63
implicit and explicit bus ownership due to the bus lock bit being set then an internal bus
request being generated.
Figure 6-38. Three-Wire Implicit and Explicit Bus Ownership
In Figure 6-38, the external master has ownership of the external bus during C1 and C2.
In C3, the external master releases control of the bus and the external arbiter asserts bus
grant (BG) to the MCF5206e. During C4 and C5, the MCF5206e is implicit owner because
an internal access is not pending and the bus lock bit in the SIMR is cleared. During C5,
the bus lock bit is set to 1, causing the MCF5206e to take explicit ownership of the bus
during C6 by asserting BD. During C7, the external arbiter removes the bus grant from the
MCF5206e by negating BG. Because the bus lock bit is set to 1, the MCF5206e does not
relinquish the bus (the MCF5206e continues to assert BD)
NOTE
The MCF5206e can start a transfer during the CLK cycle after
BG is asserted. The external arbiter should not assert BG to
the MCF5206e until the previous external master has stopped
driving the bus. BG cannot be asserted while another external
master transfer is still in progress or damage to the part could
occur.
CLK
TS
TRANSFER
TA
D[31:0]
A[27:0]
AT TR IBUT ES
BG
BD
EXTERNAL
MASTER
MCF5206e
BUS LOCK BIT
EXPLICIT OWNERSHIP
IMPLICIT
OWNERSHIP
BR
C1 C2
C3 C4 C5
C6 C7 C8 C9
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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