Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL xv
11.3.1 Reset Operation .......................................................................11-4
11.3.1.1 Master Reset ................................................................11-5
11.3.1.2 Normal Reset ................................................................11-5
11.3.2 Definition of DRAM Banks ........................................................11-5
11.3.2.1 Base Address and Address Masking ............................11-5
11.3.2.2 Access Permissions ......................................................11-7
11.3.2.3 Timing ...........................................................................11-8
11.3.2.4 Page Mode ...................................................................11-8
11.3.2.5 Port Size/Page Size ......................................................11-8
11.3.2.6 Address Multiplexing .....................................................11-8
11.3.3 Normal Mode Operation .........................................................11-15
11.3.3.1 Nonburst Transfer In Normal Mode ............................11-16
11.3.3.2 Burst Transfer In Normal Mode ..................................11-18
11.3.4 Fast Page Mode Operation ....................................................11-21
11.3.4.1 Burst Transfer In Fast Page Mode ..............................11-21
11.3.4.2 Page Hit Read Transfer In Fast Page Mode ...............11-23
11.3.4.3 Page-Hit Write Transfer in Fast Page Mode ...............11-25
11.3.4.4 Page Miss Transfer in Fast Page Mode .....................11-27
11.3.4.5 Bus Arbitration ............................................................11-30
11.3.5 Burst Page-Mode Operation ...................................................11-32
11.3.6 Extended Data-Out (EDO) DRAM Operation .........................11-35
11.3.7 Refresh Operation ..................................................................11-38
11.3.8 External Master Use of the DRAM Controller .........................11-40
11.3.8.1 External Master Nonburst Transfer in Normal Mode ..11-41
11.3.8.2 External Master Burst Transfer in Normal Mode ........11-44
11.3.8.3 External Master Burst Transfer in Burst Page Mode ..11-47
11.3.8.4 Limitations ...................................................................11-50
11.4 Programming Model .........................................................................11-50
11.4.1 DRAM Controller Registers Memory Map ..............................11-50
11.4.2 DRAM Controller Registers ....................................................11-51
11.4.2.1 DRAM Controller Refresh Register (DCRR) ...............11-51
11.4.2.2 DRAM Controller Timing Register (DCTR) .................11-52
11.4.2.3 DRAM Controller Address Reg. (DCAR0 - DCAR1) ...11-58
11.4.2.4 DRAM Controller Mask Reg. (DCMR0 - DCMR1) ......11-59
11.4.2.5 DRAM Controller Control Reg. (DCCR0 - DCCR1) ....11-60
11.5 DRAM Initialization Example ............................................................11-61
Section 12
UART Modules
12.1 Module Overview ................................................................................12-2
12.1.1 Serial Communication Channel ................................................12-2
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eescale S
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