Datasheet

Bus Operation
6-64 MCF5206e USER’S MANUAL MOTOROLA
When the bus has been removed from the MCF5206e, one of two situations can occur. In
the first case, the bus lock bit in the SIMR is cleared and the MCF5206e has explicit
ownership of the bus. When the external bus master negates BG, the MCF5206e
completes the current transfer, then negates BD and three-states the address, data, TS,
R/W, and SIZ signals after completing the current bus cycle.
In the second case, the bus lock bit in the SIMR is set to 1 and the MCF5206e has explicit
ownership of the bus. In this case, when the external bus master negates BG, the
MCF5206e continues to assert BD and continues to drive address, attributes, and control
signals. The MCF5206e retains mastership of the bus until the bus lock bit in the SIMR is
cleared. By asserting the bus lock bit, you can select the MCF5206e to be the highest
priority master, even when mastership of the bus is controlled by an external arbiter. In
this fashion, the MCF5206e can be guaranteed mastership of the bus when executing
time-critical, bus-intensive operations. Figure 6-39 illustrates bus arbitration using the bus
lock bit to control the arbitration.
Figure 6-39. Three-Wire Bus Arbitration with Bus Lock Bit Asserted
In Figure 6-39, the external master is owner of the external bus during C1 and C2. During
C2, the MCF5206e requests the external bus due to a pending internal transfer. On Clock
C3, the external master relinquishes control of the bus and the external arbiter grants the
bus to the MCF5206e by asserting bus grant (BG). At this point the bus lock bit is set to
1, and there is an internal access pending so the MCF5206e asserts bus driven (BD)
during Clock C4, and begins the access. Thus, the MCF5206e becomes the explicit
CLK
TS
TRANSFER
TA
D[31:0]
A[27:0]
AT TRIB UT ES
BG
BD
EXTERNAL
MASTER MCF5206e
EXTERNAL
MASTER
BUS LOCK BIT
BR
C1
C2 C3 C4 C5
C6
C7 C8 C9
Fr
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Freescale Semiconductor, Inc.
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