Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-67
MCF5206e can assert memory control signals (i.e., CS[7:0], WE[3:0], RAS[1:0] or
CAS[3:0]) TA and BR during this state.
The implicit ownership state indicates that the MCF5206e owns the bus because bus
grant (BG) is asserted to it. The MCF5206e, however, is not ready to begin a bus cycle
and the bus lock bit in the SIMR is cleared, and it keeps the bus three-stated until an
internal bus request occurs or the bus lock bit in the SIMR is set to 1.
The MCF5206e explicitly owns the bus when the bus is granted to it (bus grant (BG)
asserted) and at least one bus cycle has initiated or the bus lock bit in the SIMR is set to
1. The MCF5206e asserts BD in this state to indicate the MCF5206e has explicit
ownership of the bus. Until bus grant (BG) is negated, the MCF5206e regains explicit
ownership of the bus whether or not active bus cycles are being executed. Once bus grant
(BG) is negated and the bus lock bit in the SIMR is cleared, the MCF5206e relinquishes
the bus at the end of the current bus cycle. When the MCF5206e is ready to relinquish the
bus, it negates BD and three-states the bus signals.
The bus arbitration state diagram for the MCF5206e three-wire bus arbitration protocol
can be used to approximate the high level behavior of the MCF5206e. It is assumed that
all TS signals in a system are tied together and each bus master’s BD and BR signals
are connected individually to the external bus arbiter. The external bus arbiter must be
careful to make sure any external bus master has relinquished the bus or will relinquish
the bus after the next rising edge of CLK before asserting bus grant (BG) to the
MCF5206e. The MCF5206e does not monitor external bus master operation regarding
bus arbitration.
NOTE
The MCF5206e can start a transfer on the rising edge of CLK
the cycle after BG is asserted. The external arbiter should not
assert BG to the MCF5206e until the previous external master
has stopped driving the bus. BG cannot be asserted while
another external master transfer is still in progress or damage
to the part could occur.
6.10 EXTERNAL BUS MASTER OPERATION
The MCF5206e can monitor bus transfers by other bus masters and can assert chip
selects, DRAM control, and transfer termination signals during these transfers. Assertion
of chip selects and DRAM control signals can occur when the bus is granted to another
bus master and TS
is asserted by the external master as an input to the MCF5206e.
NOTE
External masters that are using internal MCF5206e chip
selects, DRAM, and default memory control signals must
initiate aligned transfers only.
Fr
eescale S
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Freescale Semiconductor, Inc.
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