Datasheet

Bus Operation
6-68 MCF5206e USER’S MANUAL MOTOROLA
The MCF5206e registers the value of A[27:0], R/W, and SIZ[1:0] on the rising edge of CLK
in which TS is asserted.
NOTE
If the pins A[27:24]/CS[7:4]/WE[0:3] are not assigned to
output address signals, a value of $0 is assigned internally to
A[27:24]. Also, TT[1:0] and ATM are not examined during
external master transfers. The mask bits SC, SD, UC, UD and
C/I in the Chip Select Mask Registers (CSMR) and in the
DRAM Controller Mask Registers (DCMR) are not used during
external master transfers.
If the assertion of chip selects, DRAM control, and transfer
termination signals during external master accesses is not
required, the MCF5206e TS pin should not be asserted when
bus driven (BD) is negated.
This subsection concentrates on external master accesses to
default memory. For more information on external master
accesses to chip select and DRAM memory spaces, refer to
Section 8 Chip Select and Section 10 DRAM Controller.
During external master transfers, the MCF5206e examines the address, direction, and
size of the transfer, and on the next rising edge of CLK, begins assertion of the proper
sequence of memory control signals. If the transfer is decoded to be a chip select address
and the chip select is enabled for the direction of the transfer (read- and/or write enabled),
the appropriate chip selects and write enable signals are asserted. If the chip select is
enabled for external master automatic acknowledge, TA is driven and asserted at the
appropriate time.
The MCF5206e does not drive addresses during external bus master accesses that are
decoded as chip select or default memory transfers. The external master must provide the
correct address to the external memory at the appropriate time. If the transfer is decoded
to be a DRAM address and the DRAM bank is enabled for the direction of the transfer
(read- and/or write enabled), the appropriate DRAM control address and the transfer-
acknowledge (TA
) signals are asserted. If the address of the transfer is neither a chip-
select or a DRAM address, the SIM reads the DMCR. If the external master automatic
acknowledge (EMAA) bit in the DMCR is set, the MCF5206e drives TA
and asserts
transfer acknowledge after the number of clocks programmed in the wait state bits (WS)
in the DMCR. For more information about programming the Default Memory Control
Register, refer to the SIM section. Table 6-13 lists the signals and conditions under which
the MCF5206e drives these signals during external master accesses.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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