Datasheet

Bus Operation

MOTOROLA MCF5206e USER’S MANUAL 6-69

6.10.1 External Master Read Transfer Using MCF5206e Termination

The basic read cycle of an external master transfer using MCF5206e-generated

termination is the same as a ColdFire core initiated transfer with one additional CLK cycle

between the assertion of TS by the external master and the starting of the internal wait-

state counter by the MCF5206e. During this CLK cycle, the MCF5206e decodes the

external master address to determine the appropriate memory control and termination

signals that must be asserted. For more information on chip select transfers and DRAM

transfers, refer to Section 8 Chip Selects and Section 10 DRAM Controller.

Figure 6-41 is a flow chart for external master read transfers using MCF5206e-generated

automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are similar for

each case and vary only with the size indicated, the portion of the data bus used for the

Table 6-14. Signal Source During External Master Accesses

MEMORY SPACE

ADDRESS

(DRIVEN BY)

CONTROL SIGNALS TRANSFER ACKNOWLEDGE

Chip Select External Master CS[7:0], WE[3:0] MCF5206e: if EMAA in CSCR is set to 1

DRAM MCF5206e: if DCAR in DCCR is

set to 1

RAS

[1:0], CAS[3:0], DRAMW MCF5206e

Default Memory External Master - MCF5206e: if EMAA in DMCR is set to

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