Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-71
Figure 6-42 illustrates transfer acknowledge (TA) assertion by the MCF5206e during
external master read transfers.
Figure 6-42. External Master Read Transfer Using MCF5206e Transfer Acknowledge
Timing (No Wait States)
Clock 1 (C1)
The read cycle starts in C1. During C1, the external master drives valid values on the
address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven
high for a read cycle, and the size signals (SIZ[1:0]) are driven to indicate the transfer size.
The external master asserts transfer start (TS
) to indicate the beginning of a bus cycle.
Clock 2 (C2)
At the start of C2, the MCF5206e registers the external master address bus, read/write
and size signals. During C2, the MCF5206e decodes the registered address and read/
write signals and if the external master automatic acknowledge (EMAA) bit in the Default
Memory Control Register (DMCR) is set to 1, the MCF5206e selects the indicated number
of wait states for loading into the internal wait state counter. During C2, the external
master negates TS
and samples the level of TA. The selected device(s) decodes the
address and drives the appropriate data onto the data bus.
Clock 3 (C3)
At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set
to 1 and the number of wait states is zero, the MCF5206e drives TA signal to the asserted
EM TS
EM A[27:0]
EM R/W
CLK
TA
D[31:0]
EM SIZ[1:0]
C1 C2 C3
C4
TEA
ATA
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