Datasheet

Bus Operation
6-72 MCF5206e USER’S MANUAL MOTOROLA
state. During C3, the external master samples the level of TA and if TA is asserted, latches
the data and terminates the transfer. If TA is negated, the external master continues to
insert wait states instead of terminating the transfer. The external master must continue
to sample TA on successive rising edges of CLK until it is asserted.
Clock 4 (C4)
During C4, the selected slave device drives the data bus to a high-impedence state. The
MCF5206e negates TA and drives TA to a high-impedence state after the next rising
edge of CLK.
6.10.2 External Master Write Transfer Using MCF5206e Termination
The basic write cycle of an external master transfer using MCF5206e-generated
termination is the same as a ColdFire core-initiated transfer with one additional CLK cycle
between the assertion of TS by the external master and the start of the internal wait state
counter by the MCF5206e. During this CLK cycle, the MCF5206e decodes the external
master address to determine the appropriate memory control and termination signals that
must be asserted. For more information on chip select transfers, refer to the Chip Selects
section. For more information on DRAM transfers, refer to the DRAM Controller section.
Figure 6-43 is a flow chart for external master write transfers using MCF5206e-generated
automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are similar for
each case and vary only with the size indicated, the portion of the data bus used for the
transfer, and the specific number of cycles needed for each transfer.
Figure 6-43. External Master Write Transfer Using MCF5206e-Generated
Transfer Acknowledge Flowchart
EXTERNAL MASTER
MCF5206e
1. DRIVE ADDRESS ON A[27:0]
2. DRIVE R/W
TO WRITE (R/W = 0)
3. DRIVE SIZ[1:0] TO INDICATE BYTE,
WORD OR LONGWORD
4. ASSERT TS
FOR ONE CLK CYCLE
1. REGISTER EXTERNAL MASTER
A[27:0], R/W, SIZ[1:0]
1. NEGATE TS
2. DRIVE DATA ON
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. RECOGNIZE THE TRANSFER
IS DONE
1. DRIVE TA TO NEGATED STATE*
2. LOAD WAIT STATE COUNTER WITH
APPROPRIATE COUNT VALUE
1. NEGATE TA FOR ONE CLK
1. THREE-STATE TA
.
1. CAPTURE THE DATA FROM
THE APPROPRIATE BYTE
LANES OF THE DATA BUS
1. THREE-STATE D[31:0]
SYSTEM
1. DECODE ADDRESS AND SELECT
THE APPROPRIATE SLAVE
DEVICE
*TA IS DRIVEN AND NEGATED IF THE APPROPRIATE WAIT STATE COUNT IS GREATER THAN ZERO. IF THE WAIT STATE COUNT IS ZERO,
T
A IS DRIVEN AND ASSERTED DURING THE SAME CLK.
1. DRIVE TA
TO ASSERTED FOR
ONE CLK CYCLE
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eescale S
emiconduct
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