Datasheet

Bus Operation
6-74 MCF5206e USER’S MANUAL MOTOROLA
the transfer. If TA is negated, the external master continues to output the data and inserts
wait states instead of terminating the transfer. The external master must continue to
sample TA on successive rising edges of CLK until it is asserted.
Clock 4 (C4)
During C4, the external master places the data bus in a high-impedence state. The
MCF5206e negates TA and drives TA to a high impedence state after the next rising edge
of CLK.
6.10.3 External Master Bursting Read Using MCF5206e-Generated
Transfer Termination
The bursting read transfer of an external master transfer using MCF5206e-generated
termination is similar to a ColdFire core initiated bursting transfer with the exception that
one additional CLK cycle is inserted between the assertion of TS by the external master
and the starting of the internal wait state counter by the MCF5206e. If the transfer is to
default memory, the external master must increment the address to the appropriate value
after each assertion of transfer acknowledge. For more information on chip select
transfers, refer to Section 8 Chip Selects. For more information on DRAM transfers, refer
to Section 10 DRAM Controller.
NOTE
An external master cannot initiate a bursting read transfer for
a chip select or default memory space where the burst-enable
bit (BRST) in the Chip Select Control Register (CSCR) or the
Default Memory Control Register (DMCR) is cleared.
Undefined behavior occurs if you attempt such a transfer.
Figure 6-45 is a flowchart for an external master bursting read transfer using MCF5206e-
generated automatic acknowledge to access 8-, 16-, or 32-bit ports. Bus operations are
similar for each case and vary only with the size indicated, the portion of the data bus used
for the transfer, and the specific number of cycles needed for each transfer. A bursting
read transfer can be from two to sixteen transfers long. The flowchart in Figure 6-45 is for
a bursting transfer four transfers long.
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