Datasheet

Bus Operation
6-76 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-46 illustrates TA assertion by the MCF5206e during external master bursting
read transfers.
Figure 6-46. External Master Bursting Longword Read Transfer to an 8-Bit Port
Using MCF5206e Transfer-Acknowledge Timing (No Wait States)
Clock 1 (C1)
The read cycle starts in C1. During C1, the external master places valid values on the
address bus (A[27:0]) and transfer control signals. The read/write (R/W) signal is driven
high for a read cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword
transfer. The external master asserts TS
to indicate the beginning of a bus cycle.
Clock 2 (C2)
At the start of C2, the MCF5206e registers the external master address bus, read/write
and size signals. During C2, the MCF5206e decodes the registered address and read/
write signals and if the external master automatic acknowledge (EMAA) bit in the Default
Memory Control Register (DMCR) is set to 1, the MCF5206e selects the indicated number
of wait states for loading into the internal wait state counter. During C2, the external
master negates TS
and samples the level of TA. The selected device(s) decodes the
address and drives the appropriate data onto the data bus.
EM TS
EM A[27:2]
EM R/W
CLK
TA
D[31:24]
EM SIZ[1:0]
C1 C2 C3
C4
C5
C6 C7
$ADDR
EM A[1:0]
$0
$0
$1
$2
$3
TEA
ATA
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
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