Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-77
Clock 3 (C3)
At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set
to 1 and the number of wait states is zero, the MCF5206e drives TA signal to the asserted
state. During C3, the external master samples the level of TA. If TA is asserted, the
external master latches the first byte of data from D[31:24]. If TA
is negated, the external
master continues to insert wait states instead of terminating the transfer. The external
master must continue to sample TA
on successive rising edges of CLK until it is asserted.
Clock 4 (C4)
During C4, the external master increments the address by one to access the second byte
of data in the longword transfer. The external master also samples the level of TA. If TA
is asserted, the external master latches the second byte of data from D[31:24]. If TA
is
negated, the external master continues to insert wait states instead of terminating the
transfer. The external master must continue to sample TA
on successive rising edges of
CLK until it is asserted.
The selected slave decodes the address and outputs the next byte of data on D[31:24].
The MCF5206e continues to assert TA.
Clock 5 (C5)
This clock is identical to C4 except the external master increments the address to point to
the third byte of data, and the selected slave decodes the address and outputs the third
byte of data of the longword transfer.
Clock 6 (C6)
This clock is identical to C4 except the external master increments the address to point to
the fourth byte of data, and the selected slave decodes the address and outputs the fourth
byte of data of the longword transfer.
Clock 7 (C7)
During C7, the selected slave device drives the data bus to a high impedence state. The
MCF5206e drives TA to the inactive state and then drives TA to a high-impedence state
after the next rising edge of CLK.
6.10.4 External Master Bursting Write Using MCF5206e-Generated
Transfer Termination
The bursting write transfer of an external master using MCF5206e-generated termination
is similar to a ColdFire core initiated bursting write transfer except that one additional CLK
cycle is inserted between the assertion of TS
by the external master and the start of the
internal wait state counter by the MCF5206e. If the transfer is to default memory, the
external master must increment the address to the appropriate value after each assertion
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