Datasheet

Bus Operation

6-78 MCF5206e USER’S MANUAL MOTOROLA

of transfer acknowledge. For more information on chip select transfers or DRAM transfers,

refer to Section 8 Chip Selects or to Section 10 DRAM Controller.

NOTE

An external master cannot initiate a bursting write transfer for

a chip select or default memory space where the burst-enable

bit (BRST) in the Chip Select Control Register (CSCR) or the

Default Memory Control Register (DMCR) is cleared.

Undefined behavior occurs if you try this.

Figure 6-47 is a flowchart for external master bursting write transfer using MCF5206e

generated automatic acknowledge to access 8-, 16- or 32-bit ports. Bus operations are

similar for each case and vary only with the size indicated, the portion of the data bus used

for the transfer and the specific number of cycles needed for each transfer. A bursting

write transfer can be from two to sixteen transfers long. The flowchart shown in Figure 6-

47 is for a bursting write transfer of four transfers long.

eescale S

emiconduct

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Freescale Semiconductor, Inc.

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