Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-79
Figure 6-47. External Master Bursting Write Transfer using MCF5206e-Generated
Transfer-Acknowledge Flowchart
EXTERNAL MASTER
MCF5206e
1. DRIVE ADDRESS ON A[27:0]
2. DRIVE R/W
TO WRITE (R/W = 0)
3. DRIVE SIZ[1:0] TO INDICATE WORD,
LONGWORD OR LINE
4. ASSERT TS
FOR ONE CLK CYCLE
1. REGISTER EXTERNAL MASTER
A[27:0], R/W
, SIZ[1:0]
1. NEGATE TS
2. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. RECOGNIZE THE 1ST TRANSFER IS
DONE
2. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON SIZ[1:0],
A[3:0] AND PORT SIZE
3. DRIVE DATA ON THE APPROPRIATE
BYTE LANES BASED ON SIZ[1:0],
A[1:0] AND PORT SIZE
1. DRIVE TA TO NEGATED STATE*
2. LOAD WAIT STATE COUNTER
WITH APPROPRIATE COUNT
VALUE
1. DRIVE TA TO
ASSERTED FOR
ONE CLK CYCLE
1. NEGATE TA
FOR ONE CLK
1. THREE-STATE TA.
1. LATCH DATA FROM THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
SYSTEM
1. DECODE ADDRESS AND
SELECT THE APPROPRIATE
SLAVE DEVICE
1. DECODE ADDRESS AND SELECT
THE APPROPRIATE SLAVE
DEVICE
2. LATCH DATA FROM THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DRIVE TA TO
ASSERTED FOR ONE
CLK CYCLE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. RECOGNIZE THE 2ND
TRANSFER IS DONE
2. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON
SIZ[1:0], A[3:0] AND PORT SIZE
3. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DECODE ADDRESS AND SELECT
THE APPROPRIATE SLAVE
DEVICE
2. LATCH DATA FROM THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. RECOGNIZE THE 3RD TRANSFER
IS DONE
2. INCREMENT APPROPRIATE
ADDRESS BITS BASED ON
SIZ[1:0], A[3:0] AND PORT SIZE
3. DRIVE DATA ON THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DECODE ADDRESS AND SELECT
THE APPROPRIATE SLAVE
DEVICE
2. LATCH DATA FROM THE
APPROPRIATE BYTE LANES
BASED ON SIZ[1:0], A[1:0] AND
PORT SIZE
1. DRIVE TA TO ASSERTED FOR
ONE CLK CYCLE
1. RECOGNIZE THE 4TH
TRANSFER IS DONE
*TA IS DRIVEN AND NEGATED IF THE APPROPRIATE WAIT STATE COUNT IS GREATER THAN ZERO. IF THE WAIT STATE COUNT IS
ZERO, TA
IS DRIVEN AND ASSERTED DURING THE SAME CLK.
1. THREE-STATE D[31:0]
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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