Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-81
Clock 3 (C3)
At the start of C3, if the EMAA bit in the Default Memory Control Register (DMCR) is set
to 1 and the number of wait states is zero, the MCF5206e asserts TA. During C3, the
external master samples the level of TA. If TA is asserted, the transfer of the first word is
complete. If TA
is negated, the external master continues to insert wait states instead of
terminating the transfer. The external master must continue to sample TA
on successive
rising edges of CLK until it is asserted.
Clock 4 (C4)
During C4, the external master increments the address by two to point to the second word
of data in the longword transfer and outputs the second word of data onto the data bus.
The external master also samples the level of TA
. If TA is asserted, the transfer of the
second word of the longword transfer is complete. If TA
is negated, the external master
continues to insert wait states instead of terminating the transfer. The external master
must continue to sample TA on successive rising edges of CLK until it is asserted.
The selected slave decodes the address and latches the next word of data on D[31:16].
The MCF5206e continues to assert TA.
Clock 5 (C5)
During C5, the external master drives the data bus to a high impedence state. The
MCF5206e drives TA to the inactive state and places TA in a high-impedence state after
the next rising edge of CLK.
6.11 RESET OPERATION
The MCF5206e supports three types of reset, two of which are external hardware resets
(master reset and normal reset) and one internal reset—Software Watchdog reset. Master
reset resets the entire MCF5206e including the DRAM controller. Normal reset resets all
of the MCF5206e with the exception of the DRAM controller. Normal reset allows DRAM
refresh cycles to continue at the programmed rate and with the programmed waveform
timing while the remainder of the system is being reset, maintaining the data stored in
DRAM. The Software Watchdog resets act as internally generated normal resets.
NOTE
Master reset must be asserted for all power-on resets. Failure
to assert master reset during power-on sequences results in
unpredictable DRAM controller behavior.
6.11.1 MASTER RESET
To perform a master reset, an external device asserts the reset input pin (RSTI) and the
HIZ input pin (HIZ) simultaneously. When power is applied to the system, external circuitry
should assert RSTI
for a minimum of six CLK cycles after Vcc is within tolerance. Figure
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