Datasheet

Bus Operation
6-82 MCF5206e USER’S MANUAL MOTOROLA
6-49 is a functional timing diagram of the master reset operation, illustrating relationships
among Vcc, RSTI, HIZ, RSTO, mode selects, and bus signals. CLK must be stable by the
time Vcc reaches the minimum operating specification. CLK should start oscillating as Vcc
is ramped up to clear out contention internal to the MCF5206e caused by the random
manner in which internal flip-flops power up. RSTI and HIZ are internally synchronized on
consecutive rising and falling clocks before being used and must meet the specified setup
and hold times to the falling edge of he clock only if recognition by a specific CLK falling
edge is required.
Figure 6-49. Master Reset Timing
TS must be pulled up or negated during master reset. When the assertion of RSTI is
recognized internally, the MCF5206e asserts the reset out pin (RSTO). RSTO is asserted
as long as RSTI
is asserted and remains asserted for 32 CLK cycles after RSTI is
negated. For proper master reset operation, RSTI
and HIZ must be asserted and negated
simultaneously.
During the master reset period, all signals that can be are driven to a high-impedence
state and all those that cannot be driven to a high-impedence state are driven to their
negated states. Once RSTI negates, all bus signals continue to remain in a high-
impedance state until the MCF5206e is granted the bus and the ColdFire core begins the
first bus cycle for reset exception processing. A master reset causes any bus cycle
(including DRAM refresh cycles) to terminate. In addition, master reset initializes registers
appropriately for a reset exception. During a master reset, the hard reset bit (HRST) bit in
the Reset Status Register (RSR) is set and the software reset bit (SRST) in the Reset
Status Register (RSR) is cleared to indicate that an external hardware reset caused the
previous reset.
VCC
RSTI
IPL[2:0]
CLK
RSTO
BUS SIGNALS
BD
BR
T >= 6
CLK CYCLES
T = 32
CLK CYCLES
T >= 22
CLK CYCLES
HIZ
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