Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-83
The levels of the IPLx pins select the port size and acknowledge features of the global chip
select after a master reset occurs. The IPLx signals are synchronized and are registered
on the last falling edge of CLK where RSTI and HIZ are asserted.
6.11.2 NORMAL RESET
External normal resets should be performed anytime it is important to maintain the data
stored in DRAM during a reset. An external normal reset is performed when an external
device asserts the reset input pin (RSTI) while negating the HIZ input pin (HIZ). During an
external normal reset, RSTI must be asserted for a minimum of six CLKs. Figure 6-50 is
a functional timing diagram of external normal reset operation, illustrating relationships
among RSTI, HIZ, RSTO, mode selects, and bus signals. RSTI and HIZ are internally
synchronized on consecutive falling and rising clocks before being used and must meet
the specified setup and hold times to the falling edge of the clock only if recognition by a
specific CLK falling edge is required.
Figure 6-50. Normal Reset Timing
TS must be pulled up or negated during normal reset. When the assertion of RSTI is
recognized internally, the MCF5206e asserts the reset out pin (RSTO
). RSTO is asserted
as long as RSTI
is asserted and remains asserted for 32 CLK cycles after RSTI is
negated. For proper normal reset operation, HIZ must be negated as long as RSTI is
asserted.
During the normal reset period, all signals that can be are driven to a high-impedence
state and all those that cannot are driven to their negated states. Once RSTI negates, all
VCC
RSTI
IPL[2:0]
CLK
RSTO
BUS SIGNALS
BD
BR
T >= 6
CLK CYCLES
T = 32
CLK CYCLES
T >= 22
CLK CYCLES
HIZ
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