Datasheet

Bus Operation
6-84 MCF5206e USER’S MANUAL MOTOROLA
bus signals continue to remain in a high-impedance state until the MCF5206e is granted
the bus and the ColdFire core begins the first bus cycle for reset exception processing.
A normal reset causes all bus activity except DRAM refresh cycles to terminate. During a
normal reset, DRAM refresh cycles continues to occur at the programmed rate and with
the programmed waveform timing. In addition, normal reset initializes registers
appropriately for a reset exception. During an external normal reset, the hard reset
(HRST) bit in the Reset Status Register (RSR) is set and the software reset (SRST) bit in
the Reset Status Register (RSR) is cleared to indicate an external hardware reset caused
the previous reset.
The levels of the IPLx pins select the port size and acknowledge features of the global
chip select after an external normal reset occurs. The IPLx signals are synchronized and
are registered on the last falling edge of CLK where RSTI is asserted.
6.11.3 SOFTWARE WATCHDOG TIMER RESET OPERATION
If the software watchdog timer is programmed to generate a reset, when a timeout occurs
an internal reset is asserted for at least 31 clocks, resetting internal registers as with a
normal reset. The RSTO pin will assert for at least 31 clocks after the software watchdog
timeout. Figure 6-51 illustrates the timing of RSTO when asserted by a software
watchdog timeout.
Figure 6-51. Software Watchdog Timer Reset Timing
NOTE
Like the normal reset, the internal reset generated by a
software watchdog timeout does not reset the DRAM
controller. DRAM refreshes continue to be generated during
CLK
RSTO
BUS SIGNALS
BD
BR
T >= 22
CLK CYCLES
SOFTWARE
INTERNAL
WATCHDOG
TIMEOUT
RESET
T >= 31
CLK CYCLES
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Freescale Semiconductor, Inc.
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