Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-85
and after the software watchdog timout reset at the
programmed rate and with the programmed waveform timing.
TS must be pulled up or negated during software watchdog reset. When the software
watchdog timeout recognized internally, the reset out pin (RTS2/RSTO) is asserted by the
MCF5206e. RSTO
is asserted for at least 31 CLK cycles after the internal software
watchdog timer reset negated.
During the software watchdog timer reset period, all signals that can be are driven to a
high-impedence state and all those that cannot are driven to their negated states. Once
RSTO negates, all bus signals continue to remain in a high-impedance state until the
MCF5206e is granted the bus and the ColdFire core begins the first bus cycle for reset
exception processing.
A software watchdog timer reset causes all bus activity except DRAM refresh cycles to
terminate. During a software watchdog timer reset, DRAM refresh cycles continue to
occur at the programmed rate and with the programmed waveform timing. In addition,
software watchdog timer reset initializes registers appropriately for a reset exception.
During a software watchdog timer reset, the hard reset (HRST) bit in the Reset Status
Register (RSR) is cleared and the software reset (SRST) bit in the Reset Status Register
(RSR) is set to 1 to indicate that a software watchdog timeout caused the previous reset.
NOTE
The levels of the IPLx pins are not sampled during a software
watchdog reset. If the port size and acknowledge features of
the global chip select are different from the values
programmed in the Chip Select Control Register 0 (CSCR0) at
the time of the software watchdog reset, you must assert RSTI
during software watchdog reset to cause the IPLx/IRQx pins
to be resampled.
Fr
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Freescale Semiconductor, Inc.
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