Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-3
• Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer
• Supports burst and cycle steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Provide two clock data transfers
7.2 DMA SIGNAL DESCRIPTION
This subsection contains a brief description of the DMA module signals used to provide
handshake control for either a source or destination external device. See Table 7-1 for
details.
Table 7-1. DMA Signals.
7.2.1 DMA Request (DREQ[1]/TOUT[0] & DREQ[0]/TIN[0])
These multiplexed pins can serve as the DMA request inputs, or as Timer 0 input and output
pins. Programming the Pin Assignment Register (PAR) in the SBC determines the function
of each of these two multiplexed pins. The pins are programmable on a bit-by-bit basis.
These active-low inputs are asserted by a peripheral device to request an operand transfer
between that peripheral and memory.
The DREQ signals are asserted to initiate DMA accesses in the respective channels. The
system should force any unused DREQ signals to a logic high state.
7.3 DMA MODULE OVERVIEW
The DMA controller module transfers data at very high rates, usually much faster than the
ColdFire core under software control can handle. The term DMA refers to a peripheral
device’s capability to access memory in a system in the same manner as a microprocessor
does. DMA operations can greatly increase overall system performance.
The DMA module consists of two independent channels, each with independent request sig-
nals.The term DMA is used throughout this section to reference either of the two channels
as they are functionally equivalent. However, both channels cannot own the bus at the same
time. Therefore, it is impossible to implicitly address both DMA channels at the same time.
The MCF5206e on-chip peripherals do not support the single-address transfer mode.
DMA requests may be internally generated by the processor writing to the start bit or exter-
nally generated by a device. The amount of bus bandwidth allocated for the DMA can be
programmed by the processor for each channel. The DMA channels support two transfer
modes: continuous mode and cycle steal mode.
SIGNAL NAME DIRECTION DESCRIPTION
DREQ[1:0] In External DMA request
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