Datasheet

DMA CONTROLLER MODULE

7-4 MCF5206e USER’S MANUAL MOTOROLA

The DMA controller supports single- and dual-address transfers. In single-address mode, a

channel supports 32 bits of address and 32 bits of data. Single-address transfers can be

started by an external device using the request signal. The DMA provides address and con-

trol signals during a single-address transfer. The requesting device either sends or receives

data to or from the specified address (see Figure 7-2). In dual-address mode, a channel sup-

ports 32 bits of address and 32 bits of data. The dual-address transfers can be started by

either the internal request mode or by an external device using the request signal. In this

mode, two bus transfers occur, one from a source device and the other to a destination

device (see Figure 7-3).

Any operation involving the DMA follows the same basic steps: channel initialization, data

transfer, and channel termination. In the channel initialization step, the DMA channel regis-

ters are loaded with control information, address pointers, and a byte transfer count. The

channel is then started. During the data transfer step, the DMA accepts requests for operand

transfers and provides addressing and bus control for the transfers. The channel termination

step occurs after operation is complete. The channel indicates the status of the operation in

the channel status register.

NOTE:

The DMA cannot access the SRAM that is resident on-chip.

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