Datasheet

DMA CONTROLLER MODULE
7-6 MCF5206e USER’S MANUAL MOTOROLA
7.4 DMA CONTROLLER MODULE PROGRAMMING MODEL
The registers of each DMA Controller Module channel are mapped into memory as shown
in Figure 7-5. The base address for each channel of the DMA Controller Module is displayed
in Table 7-7.
The DMA Controller Module register set controls the DMA Controller Module. This section
describes each of the internal registers and the bit assignment for each register. Note that
there is no mechanism for the prevention of writes to control registers during DMA transfers.
7.4.1 Source Address Register (SAR)
The source address register (SAR) is a 32-bit register containing the address from which the
DMA Controller Module will request data during a transfer. In Single Address Mode, the SAR
provides the address regardless of the direction.
Source Address Register (SAR)
Base Address Offset Channel
MBAR + DMA0SAR Channel 0
MBAR + DMA1SAR Channel 1
Table 7-2. DMA Controller Module Channel Offsets
Base
Address
Offset
[31:0]
$200 Source Address Register 0
$204 Destination Address Register 0
$208 DMA Control Register 0 Reserved
$20C Byte Count Register 0 Reserved
$210 Status Register 0 Reserved
$214 Interrupt Vector Register 0 Reserved
$240 Source Address Register 1
$244 Destination Address Register 1
$248 DMA Control Register 1 Reserved
$24C Byte Count Register 1 Reserved
$250 Status Register 1 Reserved
$254 Interrupt Vector Register 1 Reserved
Figure 7-4. DMA Controller Module Register Model Per Channel
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR31 SAR30 SAR29 SAR28 SAR27 SAR26 SAR25 SAR24 SAR23 SAR22 SAR21 SAR20 SAR19 SAR18 SAR17 SAR16
Reset:
0000000000000000
1514131211109876543210
SAR15 SAR14 SAR13 SAR12 SAR11 SAR10 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0
Reset:
0000000000000000
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