Datasheet

DMA CONTROLLER MODULE
MOTOROLA MCF5206e USER’S MANUAL 7-7
7.4.2 Destination Address Register (DAR)
The destination address register (DAR) is a 32-bit register containing the address to which
the DMA Controller Module will send data during a transfer. Note that this register is only
used during dual address transfers.
Destination Address Register (DAR)
7.4.3 Byte Count Register (BCR)
The byte count register (BCR) is a 16-bit register containing the number of bytes remaining
to be transferred for a given block. The BCR count is the number of bytes remaining to be
written.
The BCR decrements on the successful completion of the address phase of either a write
transfer in dual address mode or any transfer in single address mode. The amount the BCR
decrements is 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
Byte Count Register (BCR)
The DONE bit in the DMA Status Register is set when the entire block transfer is complete,
when BCR = $00.
When a transfer sequence is initiated and the BCR contains a value that is not divisible by
16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively,
the configuration error bit in the DMA status register (DSR) is set and the transfer is not
performed.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR31 DAR30 DAR29 DAR28 DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 DAR20 DAR19 DAR18 DAR17 DAR16
Reset:
0000000000000000
1514131211109876543210
DAR15 DAR14 DAR13 DAR12 DAR11 DAR10 DAR9 DAR8 DAR7 DAR6 DAR5 DAR4 DAR3 DAR2 DAR1 DAR0
Reset:
0000000000000000
1514131211109876543210
BCR15 BCR4 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
Reset:
0000000000000000
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