Datasheet

DMA CONTROLLER MODULE
7-8 MCF5206e USER’S MANUAL MOTOROLA
7.4.4 DMA Control Register
The DMA control register (DCR) is a 16-bit register that controls the configuration of the
DMA Controller Module.
DMA Control Register (DCR)
INT—Interrupt on completion of transfer
This field controls whether an interrupt is to be generated at the completion of the transfer
or occurrence of an error condition.
1 = SINT asserts. An internal interrupt signal asserts at the completion of a transfer.
0 = No interrupt is generated.
EEXT—Enable External DMA Request
1 = Enables the external request signal to affect transfer initiation. The START bit is al-
ways enabled.
0 = The external request is ignored.
NOTE
There is no logic precluding collisions with START bit and DREQ
signal except for EEXT. Use caution when initiating a DMA
transfer with the START bit while EEXT=1.
CS—Cycle Steal
1 = Forces a single read/write transfer per request. The request may be internal by set-
ting the START bit, or external by asserting the DREQ signal.
0 = The DMA performs continuous read/write transfers until the BCR decrements to 0
or until the boundary defined by the BWC bits is reached.
AA—Auto-Align
This bit and the size bits determine whether the source or destination is auto-aligned. Auto
alignment means that the accesses are optimized based on the address value and the
programmed size. For more information see 7.10.2.2 Auto Alignment.
1 = If the SSIZE bits indicate a larger or equivalent transfer size with respect to DSIZE,
then the source accesses are auto-aligned. If the DSIZE bits indicate a larger trans-
fer size than SSIZE, then the destination accesses are auto-aligned. Source align-
ment takes precedence over destination alignment. If auto-alignment is enabled,
the appropriate address register increments, regardless of the state of DINC or
SINC.
0 = No accesses are auto aligned
1514131211109876543210
INT EEXT CS AA BWC SAA S_RW SINC SSIZE DINC DSIZE START
Reset:
0000000000000000
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